/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** ************************************************************************************************
 * \file     Firewall_Mpc.c                                                                   *
 * \brief    Semidrive Firewall MPC Driver                                                              *
 *                                                                                                 *
 **************************************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************************************************
 *                                      Include header files                                       *
 **************************************************************************************************/
#if (defined(CFG_PLATFORM_MCAL))
#include "RegHelper.h"
#endif /** #if (defined(CFG_PLATFORM_MCAL)) */

#include "Firewall_Mpc_Ip.h"

/***************************************************************************************************
 *                                 Private Macro definition                                        *
 **************************************************************************************************/
/** \brief The address offset of the domain0 ~ 3 permissions register
 *         for the different memory port.
 */
#define MPC_DOM_PER0(n)        ((uint32_t)((uint32_t)(n)*0x10U))
/** \brief The address offset of the domain4 ~ 7 permissions register
 *         for the different memory port.
 */
#define MPC_DOM_PER1(n)        ((uint32_t)(0x4U + ((uint32_t)(n)*0x10U)))
/** \brief The address offset of the domain8 ~ 11 permissions register
 *         for the different memory port.
 */
#define MPC_DOM_PER2(n)        ((uint32_t)(0x8U + ((uint32_t)(n)*0x10U)))
/** \brief The address offset of the domain12 ~ 15 permissions register
 *         for the different memory port.
 */
#define MPC_DOM_PER3(n)        ((uint32_t)(0xCU + ((uint32_t)(n)*0x10U)))

/** \brief The address offset of the permission lock register. */
#define MPC_DOM_PER_LOCK(n)    ((uint32_t)(0x100U + ((uint32_t)(n)*0x4U)))
/** \brief The mask of the permission lock. */
#define MPC_DOM_PER_LOCK_MASK  (0xFFFFU)

/** \brief The bit offset of the domain0. */
#define DOM_PER_DOMAIN0_BIT    (4U)
/** \brief The bit offset of the domain1. */
#define DOM_PER_DOMAIN1_BIT    (8U + 4U)
/** \brief The bit offset of the domain2. */
#define DOM_PER_DOMAIN2_BIT    (16U + 4U)
/** \brief The bit offset of the domain3. */
#define DOM_PER_DOMAIN3_BIT    (24U + 4U)
/** \brief The bit offset of the domain4. */
#define DOM_PER_DOMAIN4_BIT    (4U)
/** \brief The bit offset of the domain5. */
#define DOM_PER_DOMAIN5_BIT    (8U + 4U)
/** \brief The bit offset of the domain6. */
#define DOM_PER_DOMAIN6_BIT    (16U + 4U)
/** \brief The bit offset of the domain7. */
#define DOM_PER_DOMAIN7_BIT    (24U + 4U)
/** \brief The bit offset of the domain8. */
#define DOM_PER_DOMAIN8_BIT    (4U)
/** \brief The bit offset of the domain9. */
#define DOM_PER_DOMAIN9_BIT    (8U + 4U)
/** \brief The bit offset of the domain10. */
#define DOM_PER_DOMAIN10_BIT   (16U + 4U)
/** \brief The bit offset of the domain11. */
#define DOM_PER_DOMAIN11_BIT   (24U + 4U)
/** \brief The bit offset of the domain12. */
#define DOM_PER_DOMAIN12_BIT   (4U)
/** \brief The bit offset of the domain13. */
#define DOM_PER_DOMAIN13_BIT   (8U + 4U)
/** \brief The bit offset of the domain14. */
#define DOM_PER_DOMAIN14_BIT   (16U + 4U)
/** \brief The bit offset of the domain15. */
#define DOM_PER_DOMAIN15_BIT   (24U + 4U)

/** \brief The address offset of the region start address register. */
#define MPC_RGN_START_ADDR(n)  (uint32_t)((0x140U + ((uint32_t)(n)*0x0CU)))
/** \brief The address offset of the region end address register. */
#define MPC_RGN_END_ADDR(n)    (uint32_t)((0x144U + ((uint32_t)(n)*0x0CU)))
/** \brief The start bit of locking region memory range. */
#define MPC_RGN_LOCK           (31U)

/** \brief The address offset of the region enable register. */
#define MPC_RGN_ADDR_ENABLE(n) (uint32_t)((0x148U + ((uint32_t)(n)*0x0CU)))
/** \brief The start bit of locking region enable configuration. */
#define MPC_RGN_ENABLE_LOCK     (31U)
/** \brief The start bit of locking region enable inverse configuration. */
#define MPC_RGN_ENABLE_LOCK_INV (30U)
/** \brief The start bit of enabling region configuration. */
#define MPC_RGN_ENABLE_INV      (1U)
/** \brief The start bit of enabling region configuration. */
#define MPC_RGN_ENABLE          (0U)

/** \brief The address offset of the response error register. */
#define MPC_RESP_ERR_DIS       ((uint32_t)0x254U)
/** \brief The bit mask of locking the response error configuration. */
#define MPC_RESP_ERR_DIS_LOCK  (0x1UL << 31U)
/** \brief The bit mask of disabling the response error feature. */
#define MPC_RESP_ERR_DIS_DIS   (0x1UL)

/** \brief The address offset of the interrupt status register. */
#define MPC_FUNC_INT_STA       (uint32_t)(0x500U)

/** \brief The address offset of the interrupt status enable register. */
#define MPC_FUNC_INT_STA_EN    ((uint32_t)0x504U)
/** \brief The address offset of the interrupt signal enable register. */
#define MPC_FUNC_INT_SIG_EN    ((uint32_t)0x508U)
/** \brief The bit mask of setting register access error. */
#define MPC_REG_ACS_ERR        (0x1U << 1U)
/** \brief The bit mask of setting memory access error. */
#define MPC_MEM_ACS_ERR        (0x1U)

/** \brief Address alignment. */
#define MPC_REGION_ADDR(addr)  ((uint32_t)(addr) >> 12U)

/** \brief The 1bit mask of MPC registers. */
#define MPC_REG_BIT1_MASK           ((uint32_t)0x1U)
/** \brief The 2bit mask of MPC registers. */
#define MPC_REG_BIT2_MASK           ((uint32_t)0x2U)
/** \brief The 1bit of MPC registers. */
#define MPC_REG_BIT1_WIDTH          (1U)
/** \brief The 2bit of MPC registers. */
#define MPC_REG_BIT2_WIDTH          (2U)

/** \brief The address offset of the response error inverse register. */
#define MPC_RESP_ERR_DIS_INV        ((uint32_t)0x258U)

/** \brief The address offset of the response error inverse register. */
#define MPC_REG_CFG_CMP_EN          ((uint32_t)0x260U)
/** \brief The start bit of locking reg compare configuration. */
#define MPC_REG_CFG_CMP_LOCK        (31U)
/** \brief The start bit of locking reg compare configuration inverse. */
#define MPC_REG_CFG_CMP_LOCK_INV    (30U)
/** \brief The srart bit of enabling reg compare configuration inverse. */
#define MPC_REG_CFG_CMP_ENABLE_INV  (1U)
/** \brief The srart bit of enabling reg compare configuration. */
#define MPC_REG_CFG_CMP_ENABLE      (0U)

/** \brief The offset of the RGN_START_ADDR_INV register. */
#define MPC_RGN_START_ADDR_INV(n)   (uint32_t)((0x27CU + ((uint32_t)(n)*0x0CU)))
/** \brief The offset of the RGN_END_ADDR_INV register. */
#define MPC_RGN_END_ADDR_INV(n)     (uint32_t)((0x278U + ((uint32_t)(n)*0x0CU)))

/** \brief The offset of the DOM_PER_LOCK_INV register. */
#define MPC_DOM_PER_LOCK_INV(n)     ((uint32_t)(0x380U + ((uint32_t)(n)*0x04U)))

/** \brief The offset of domain 0~3 permissions inverse register. */
#define MPC_DOM_PER0_INV(n)         ((uint32_t)(0x40CU + ((uint32_t)(n)*0x10U)))
/** \brief The offset of domain 4~7 permissions inverse register. */
#define MPC_DOM_PER1_INV(n)         ((uint32_t)(0x408U + ((uint32_t)(n)*0x10U)))
/** \brief The offset of domain 8~11 permissions inverse register. */
#define MPC_DOM_PER2_INV(n)         ((uint32_t)(0x404U + ((uint32_t)(n)*0x10U)))
/** \brief The offset of domain 12~15 permissions inverse register. */
#define MPC_DOM_PER3_INV(n)         ((uint32_t)(0x400U + ((uint32_t)(n)*0x10U)))

#if (defined(CFG_PLATFORM_MCAL))
#define FIREWALL_START_SEC_CODE
#include "Firewall_MemMap.h"
#endif /** #if (defined(CFG_PLATFORM_MCAL)) */

/***************************************************************************************************
 *                                  Global Function Declarations                                   *
 **************************************************************************************************/
/**
 * \brief Configure the permission of memory port regions in MPC module.
 *
 * This function configure memory ports in MPC module.
 * The permissions of memory regions in MPC module should be locked after
 * configuring.
 *
 * \param[in] ctrl the firewall instance.
 * \param[in] mpc_cfg  The configuration of memory.
 * \param[in] memport_num  The number of memory port.
 *
 * \return The result of the MPC initialization function.
 * \details - return FIREWALL_E_OK : initializa MPC success.
 *          - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
 *          - return FIREWALL_E_MPC_PORT_NUM : The number of memory port is
 * unvalid.
 */
lld_status_t Firewall_MpcConfigure(const Firewall_ControllerType *ctrl,
                                     const Firewall_MpcMemPortConfigType *mpc_cfg,
                                     uint32_t memport_num)
{
    lld_status_t ret_val = (lld_status_t)FIREWALL_E_OK;
    uint32_t base = ctrl->macBaseAddr;
    uint8_t port_num;

    /* #10 Check the parameters. */
    if (NULL == mpc_cfg)
    {
        ret_val = (lld_status_t)FIREWALL_E_NULL_POINTER;
    }
    else if (FIREWALL_MPC_MEMPORT_MAXNUM < memport_num)
    {
        ret_val = (lld_status_t)FIREWALL_E_MPC_PORT_NUM;
    }
    else
    {
        for (port_num = 0; port_num < memport_num; port_num++)
        {
            /* #20 Configure all regions of the memory port. */
            ret_val = Firewall_MpcRegionConfigure(base, &mpc_cfg[port_num]);
            if ((lld_status_t)FIREWALL_E_OK != ret_val)
            {
                break;
            }

            if (1U == ctrl->interruptEnable)
            {
                /* #30 Turn on inturrupt when illegal access. */
                writel(MPC_REG_ACS_ERR | MPC_MEM_ACS_ERR,
                    base + mpc_cfg[port_num].mpcBaseOffset + MPC_FUNC_INT_STA_EN);
                writel(MPC_REG_ACS_ERR | MPC_MEM_ACS_ERR,
                    base + mpc_cfg[port_num].mpcBaseOffset + MPC_FUNC_INT_SIG_EN);
            }

            if (1U != ctrl->resErrEnable)
            {
                /* #40 Disable respone error when illegal access, and lock this
                 * configuration. */
                writel(MPC_RESP_ERR_DIS_DIS,
                    base + mpc_cfg[port_num].mpcBaseOffset + MPC_RESP_ERR_DIS);
                writel(MPC_RESP_ERR_DIS_DIS | MPC_RESP_ERR_DIS_LOCK,
                    base + mpc_cfg[port_num].mpcBaseOffset + MPC_RESP_ERR_DIS);

                /* Write inverse registers for safety mechanism. */
                writel(~(MPC_RESP_ERR_DIS_DIS),
                    base + mpc_cfg[port_num].mpcBaseOffset + MPC_RESP_ERR_DIS_INV);
                writel(~(MPC_RESP_ERR_DIS_DIS | MPC_RESP_ERR_DIS_LOCK),
                    base + mpc_cfg[port_num].mpcBaseOffset + MPC_RESP_ERR_DIS_INV);
            }

            /* #50 Enable and lock MPC register compare for safety mechanism. */
            RMWREG32(base + mpc_cfg[port_num].mpcBaseOffset + MPC_REG_CFG_CMP_EN,
                MPC_REG_CFG_CMP_ENABLE, MPC_REG_BIT2_WIDTH, MPC_REG_BIT1_MASK);

            RMWREG32(base + mpc_cfg[port_num].mpcBaseOffset + MPC_REG_CFG_CMP_EN,
                MPC_REG_CFG_CMP_LOCK_INV, MPC_REG_BIT2_WIDTH, MPC_REG_BIT2_MASK);

        }
    }

    return ret_val;
}

/**
 * \brief Handle the interrupt status of the MPC module.
 *
 * This function get the illegal access error information of the MPC module.
 * The function exits as soon as it gets an illegal access message.
 * This function should be called by the firewall interrupt handler
 * Firewall_IrqHandler().
 *
 * \param[in] base the address of the MAC module.
 * \param[in] mpc_cfg  The configuration of memory.
 * \param[in] memport_num  The number of memory port.
 * \param[out] mpc_irqsta  The status of mpc interrupt.
 *
 * \return The result of the MPC handler.
 * \details - return FIREWALL_E_OK : Handle MPC interrupt success.
 *          - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
 *          - return FIREWALL_E_MPC_PORT_NUM : The number of memory port is
 * unvalid.
 */
lld_status_t Firewall_MpcIrqHandler(uint32_t base,
                                       const Firewall_MpcMemPortConfigType *mpc_cfg,
                                       uint32_t memport_num,
                                       Firewall_MpcIrqStaType *mpc_irqsta)
{
    lld_status_t ret_val = (lld_status_t)FIREWALL_E_OK;
    uint8_t port_num;
    uint32_t sta_enable;
    uint32_t sig_enable;
    uint32_t port_base;

    /* #10 Check the parameters. */
    if ((NULL == mpc_cfg) || (NULL == mpc_irqsta))
    {
        ret_val = (lld_status_t)FIREWALL_E_NULL_POINTER;
    }
    else if (FIREWALL_MPC_MEMPORT_MAXNUM < memport_num)
    {
        ret_val = (lld_status_t)FIREWALL_E_MPC_PORT_NUM;
    }
    else
    {
        /* #20 Get the illegal access information from the MPC module interrupt.
         */
        for (port_num = 0U; port_num < memport_num; ++port_num)
        {
            /* Get the interrupt status of the memory port. */
            port_base = base + mpc_cfg[port_num].mpcBaseOffset;
            mpc_irqsta->mpcErrSta = readl(port_base + MPC_FUNC_INT_STA);

            if (0U < mpc_irqsta->mpcErrSta)
            {
                /* Clear the interrupt status of the memory port. */
                writel(mpc_irqsta->mpcErrSta, port_base + MPC_FUNC_INT_STA);

                sta_enable = readl(port_base + MPC_FUNC_INT_STA_EN);
                sig_enable = readl(port_base + MPC_FUNC_INT_SIG_EN);
                if (0U == ((uint32_t)mpc_irqsta->mpcErrSta & sta_enable &
                           sig_enable))
                {
                    mpc_irqsta->mpcErrSta = 0U;
                }
                else
                {
                    mpc_irqsta->mpcMemPortId = port_num;
                }

                break;
            } /* else not needed */
        }
    }

    return ret_val;
}

/**
 * \brief Clear the interrupt status of the MPC module.
 *
 * This function will clear the interrupt registers in the MPC module.
 * This function should not be called after the firewall has been initialized.
 *
 * \param[in] base the address of the MAC module.
 * \param[in] mpc_cfg  The configuration of memory.
 * \param[in] memport_num  The number of memory port.
 */
void Firewall_MpcClearInterrupt(uint32_t base,
    const Firewall_MpcMemPortConfigType *mpc_cfg, uint32_t memport_num)
{
    uint32_t port_base;
    uint8_t portNum;

    /* #10 Check if Mpc port number smaller than MAXPORT NUM. */
    if (FIREWALL_MPC_MEMPORT_MAXNUM >= memport_num)
    {
        /* #20 Clear the interrupt of all memory ports. */
        for (portNum = 0U; portNum < memport_num; ++portNum)
        {
            port_base = base + mpc_cfg[portNum].mpcBaseOffset;
            /* Disable the interrupt of the memory port. */
            writel(FIREWALL_REG_VALUE_MIN, port_base + MPC_FUNC_INT_STA_EN);
            /* Disable the interrupt signal of the memory port. */
            writel(FIREWALL_REG_VALUE_MIN, port_base + MPC_FUNC_INT_SIG_EN);
            /* Clear the interrupt status of the memory port. */
            writel(FIREWALL_REG_VALUE_MAX, port_base + MPC_FUNC_INT_STA);
        }
    }
}

/**
 * \brief Control the interrupt of the MPC module.
 *
 * This function enable/disable the interrupt of illegal accessing for the MPC module.
 *
 * \param[in] base the address of the MAC module.
 * \param[in] mpc_cfg The pointer to memory ports configuration
 * \param[in] memport_num The number of memory ports
 * \param[in] enable Enable or disable the interrupts
 */
void Firewall_MpcInterruptEnable(uint32_t base, const Firewall_MpcMemPortConfigType *mpc_cfg,
                                        uint32_t memport_num, bool enable)
{
    uint8_t port_num;
    uint32_t sta_val;
    uint32_t sig_val;

    /* #10 Check inturrupt enable status. */
    sta_val = (true == enable) ? (uint32_t)(MPC_REG_ACS_ERR | MPC_MEM_ACS_ERR) : 0U;
    sig_val = (true == enable) ? (uint32_t)(MPC_REG_ACS_ERR | MPC_MEM_ACS_ERR) : 0U;
    for (port_num = 0U; port_num < memport_num; ++port_num)
    {
            /* #20 Turn on inturrupt when illegal access. */
            writel(sta_val, base + mpc_cfg[port_num].mpcBaseOffset + MPC_FUNC_INT_STA_EN);
            writel(sig_val, base + mpc_cfg[port_num].mpcBaseOffset + MPC_FUNC_INT_SIG_EN);
    }
}

/**
 * brief Configure the permission of memory regions in MPC module.
 *
 * This function will be called by Firewall_MpcConfigure().
 *
 * param[in] base the address of the MAC module.
 * param[in] memory the address of the MPC port configuration.
 *
 * return The result of the configuration.
 * details - return FIREWALL_E_OK : initializa MPC regions success.
 *          - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
 *          - return FIREWALL_E_MPC_REGION_NUM : The number of regions in the
 *                                               port is unvalid.
 */
lld_status_t Firewall_MpcRegionConfigure(uint32_t base,
                               const Firewall_MpcMemPortConfigType *memory)
{
    lld_status_t ret_val = (lld_status_t)FIREWALL_E_OK;
    const Firewall_MpcRegionConfigType *region;
    uint32_t port_base;
    uint32_t temp_val;
    uint8_t num;

    /* #10 Check the parameters. */
    if (NULL == memory)
    {
        ret_val = (lld_status_t)FIREWALL_E_NULL_POINTER;
    }
    else if (Firewall_MpcGetRegionMaxNum(memory->mpcBaseOffset) < memory->mpcRegionNum)
    {
        ret_val = (lld_status_t)FIREWALL_E_MPC_REGION_NUM;
    }
    else
    {
        port_base = base + memory->mpcBaseOffset;
        /* #20 Configure all regions of the memory port. */
        for (num = 0; num < memory->mpcRegionNum; num++)
        {
            if (MPC_DOM_PER_LOCK_MASK == (MPC_DOM_PER_LOCK_MASK &
                                        readl(port_base + MPC_DOM_PER_LOCK(num))))
            {
                continue;
            }

            region = &memory->mpcRegionCfgPtr[num];

            /* Configure domain 0-3 permission. */
            temp_val = (uint32_t)region->mpcDomain0Permission << DOM_PER_DOMAIN0_BIT;
            temp_val |= (uint32_t)region->mpcDomain1Permission << DOM_PER_DOMAIN1_BIT;
            temp_val |= (uint32_t)region->mpcDomain2Permission << DOM_PER_DOMAIN2_BIT;
            temp_val |= (uint32_t)region->mpcDomain3Permission << DOM_PER_DOMAIN3_BIT;
            writel(temp_val, port_base + MPC_DOM_PER0(num));
            writel((~temp_val), port_base + MPC_DOM_PER0_INV(num));

            /* Configure domain 4-7 permission. */
            temp_val = (uint32_t)region->mpcDomain4Permission << DOM_PER_DOMAIN4_BIT;
            temp_val |= (uint32_t)region->mpcDomain5Permission << DOM_PER_DOMAIN5_BIT;
            temp_val |= (uint32_t)region->mpcDomain6Permission << DOM_PER_DOMAIN6_BIT;
            temp_val |= (uint32_t)region->mpcDomain7Permission << DOM_PER_DOMAIN7_BIT;
            writel(temp_val, port_base + MPC_DOM_PER1(num));
            writel((~temp_val), port_base + MPC_DOM_PER1_INV(num));

            /* Configure domain 8-11 permission. */
            temp_val = (uint32_t)region->mpcDomain8Permission << DOM_PER_DOMAIN8_BIT;
            temp_val |= (uint32_t)region->mpcDomain9Permission << DOM_PER_DOMAIN9_BIT;
            temp_val |= (uint32_t)region->mpcDomain10Permission << DOM_PER_DOMAIN10_BIT;
            temp_val |= (uint32_t)region->mpcDomain11Permission << DOM_PER_DOMAIN11_BIT;
            writel(temp_val, port_base + MPC_DOM_PER2(num));
            writel((~temp_val), port_base + MPC_DOM_PER2_INV(num));

            /* Configure domain 12-15 permission. */
            temp_val = (uint32_t)region->mpcDomain12Permission << DOM_PER_DOMAIN12_BIT;
            temp_val |= (uint32_t)region->mpcDomain13Permission << DOM_PER_DOMAIN13_BIT;
            temp_val |= (uint32_t)region->mpcDomain14Permission << DOM_PER_DOMAIN14_BIT;
            temp_val |= (uint32_t)region->mpcDomain15Permission << DOM_PER_DOMAIN15_BIT;
            writel(temp_val, port_base + MPC_DOM_PER3(num));
            writel((~temp_val), port_base + MPC_DOM_PER3_INV(num));

            /* Lock the permission configuration of all regions. */
            temp_val = readl(port_base + MPC_DOM_PER_LOCK(num));
            writel(temp_val | MPC_DOM_PER_LOCK_MASK, port_base + MPC_DOM_PER_LOCK(num));
            writel((~(temp_val | MPC_DOM_PER_LOCK_MASK)),
                        port_base + MPC_DOM_PER_LOCK_INV(num));

            /* Configure the address range of the region. */
            writel(MPC_REGION_ADDR(region->mpcStartAddr),
                   port_base + MPC_RGN_START_ADDR(num));
            writel((~MPC_REGION_ADDR(region->mpcStartAddr)),
                   port_base + MPC_RGN_START_ADDR_INV(num));

            writel(MPC_REGION_ADDR(region->mpcEndAddr),
                   port_base + MPC_RGN_END_ADDR(num));
            writel((~MPC_REGION_ADDR(region->mpcEndAddr)),
                   port_base + MPC_RGN_END_ADDR_INV(num));

            /* Lock the address range of the region. */
            RMWREG32(port_base + MPC_RGN_END_ADDR(num),
                    MPC_RGN_LOCK, MPC_REG_BIT1_WIDTH, MPC_REG_BIT1_MASK);
            RMWREG32(port_base + MPC_RGN_END_ADDR_INV(num),
                    MPC_RGN_LOCK, MPC_REG_BIT1_WIDTH,
                                ((~MPC_REG_BIT1_MASK) & MPC_REG_BIT1_MASK));

            /* Enable and lock the region's configuration. */
            RMWREG32(port_base + MPC_RGN_ADDR_ENABLE(num),
                    MPC_RGN_ENABLE, MPC_REG_BIT2_WIDTH, MPC_REG_BIT1_MASK);

            RMWREG32(port_base + MPC_RGN_ADDR_ENABLE(num),
                    MPC_RGN_ENABLE_LOCK_INV, MPC_REG_BIT2_WIDTH, MPC_REG_BIT2_MASK);
        }
    }

    return ret_val;
}

#if (defined(CFG_PLATFORM_MCAL))
#define FIREWALL_STOP_SEC_CODE
#include "Firewall_MemMap.h"
#endif /** #if (defined(CFG_PLATFORM_MCAL)) */

#ifdef __cplusplus
}
#endif

/* End of file */
